1. Field of the Invention
This disclosure relates generally to methods and apparatuses for calibrating clocks in clocked digital devices.
2. Description of the Related Art
Many modern electronic devices operate based on clock signals that are provided to the device from an external source and/or generated internal to the electronic devices. Such devices are referred to herein as clocked digital devices.
Because of their nature, clocked digital devices can and do exhibit a range of different performance characteristics based on the manufacturing and operating conditions associated with the devices. For example, multiple units of the same model of a clocked digital device may exhibit different operating characteristics due to variance in the processes used to create the units and in the characteristics of the materials used in the manufacturing processes. As another example, the same unit of a given clocked digital device can exhibit a first set of operating characteristics when operating at a first voltage and a second set of operating characteristics when operating at a second voltage. Still further, the same unit of a given clocked digital device can exhibit one set of operating characteristics when operating at a first temperature and a different set of operating characteristics when operating at a second temperature.
One set of operating characteristics that can vary depending on process, voltage, and/or temperature is the set of characteristics related to the timing performance of a clocked digital device. One such exemplary characteristic is the precise amount of time required for a clocked digital device to provide a valid output signal after receiving an active edge on a clock signal whose transitions produce the output in question. Another such exemplary characteristic is the precise length of time that an input to a clocked digital device must remain stable (in the same logical state) prior to receipt of an active edge on a clock signal used to capture (receive) the input signal. Yet another exemplary characteristic is the precise length of time that an input to a clocked digital device must remain stable (in the same logical state) following receipt of an active edge on a clock signal used to capture the input signal. Each of these exemplary characteristics, as well as other characteristics of a clocked digital device, can vary depending on process, voltage, temperature, or other operating characteristics.
Because of the variability of clocked digital devices, adjustments must often be made that can reduce the predictability and/or performance of systems including such devices. For example, in an ideal situation, a clocked digital device intended to capture a digital input signal in response to a given clock signal would capture the input digital signal precisely at the active edge of the clock signal. This ideal situation is illustrated in FIG. 1A, which depicts a clock signal 100 with the active edge defined to be the rising (low-to-high) edge of the clock signal. Also illustrated in FIG. 1A are lines 110 representing the time interval during which valid data must be present at the input to the idealized clocked digital device in order to facilitate proper reception of the input signal. Because it is assumed in this example that the clocked digital device samples its input precisely at the active edge of the clock, there is only a very limited period of time (ideally a time interval of 0 centered at exactly the low-to-high transition point of the clock signal) during which the input data must be valid.
In practice, clocked digital devices are not ideal. As such, a clocked digital device will not sample its input value precisely at the active edge of the externally-generated clock supplied to the device. In real operation, the input data may ultimately be sampled at a point that occurs either earlier or later in time relative to the active edge of the relevant clock. Moreover, because of variations in manufacturing processes, construction materials, temperature, voltage, and other operating conditions, the precise time at which a clocked digital device samples an input will not typically be consistent, but will vary from unit to unit, device to device, and from one operating condition (e.g., temperature or voltage) to another operating condition for a given unit or device.
To account for the variable operating conditions as described, it is often necessary to regulate and control the manner in which such devices are used. For example, in the above example, it was noted that the actual time at which a given clocked digital device may sample a desired input can vary from a time prior to the active edge of the relevant clock to a time after the active edge of the relevant clock. Thus, to ensure that such a device consistently receives valid data, it will be necessary to ensure that the inputs to the device remain valid and constant for a time interval spanning all possible sampling points. This time interval must begin before the active clock edge (in case the sampling occurs earlier) and end after the active clock edge (in case the input is sampled later).
The time interval during which an input to a device must remain valid and stable prior to the receipt of an active edge of the relevant clock is commonly referred to as the “setup time” and is often designated as Tsu. The time period after the active clock edge during which the input to a device must remain valid and stable is commonly referred to as the “hold time” and is often designated Th. FIG. 1B illustrates an exemplary Tsu time 120 and Th time 130 for one input of a clocked digital device with respect to exemplary clock signal 100. Tsu and Th may be negative quantities. A positive setup time and negative hold time defines a time interval prior to the active edge of the relevant clock. Likewise, a negative setup time and positive hold time defines a time interval after the active edge of the relevant clock. Based upon the preceding definition of Tsu and Th, a given input signal should not simultaneously exhibit negative values for both Tsu and Th.
Another important operating parameter for a digital device is commonly known as the clock-to-output time, often designated Tco. For a given output of a clocked digital device and a given clock signal, Tco typically represents the longest expected amount of time required for a valid output signal to appear following the active edge of the given clock. Like the Tsu and the Th values, the value of Tco for a given clocked digital device is subject to variation as a result of process, voltage, temperature and other operating conditions. Tco may also be a negative quantity, although this will occur only when an “early” version of the clock signal is available inside of the device, e.g. when using a phase-locked loop (PLL) or other similar clock management resource. A negative Tco value does not imply a non-causal relationship between an output signal and its corresponding clock.
Ideally the Tsu and Th values for a clocked digital device's inputs, and the Tco value for its outputs, would be zero. Practically, however, these values are set to account for the maximum range of possible delays that the associated clocked digital device may encounter in expected operation. As a result, to ensure predictable and robust operations, systems utilizing such devices must typically account for the range of potential operating conditions, which generally results in slower system operation than would be possible if the Tsu, Th and Tco values were at, or nearly at zero, and if the Tsu, Th and Tco values were not subject to variation as a result of differing manufacturing and/or operating conditions. Accordingly, there is a need and benefit to providing apparatuses and methods that can dynamically control and adjust the Tsu, Th and Tco values to compensate for operation and manufacturing variations and to hold the values of Tsu, Th, and Tco constant, independent of those variations.
Because of the potential benefits of having the output of a clocked digital device be valid at, or shortly after, the active edge of the relevant clock, attempts have been made to develop and utilize active circuits to try to provide some form of clock-to-output time or Tco compensation to try to ensure that the apparent clock-to-output time, Tco, for a device including the circuit is equal to zero, as determined from the active clock edge. If the relevant clock signal is free-running and periodic, then similar benefits may also be obtained from the less stringent requirement that Tco be an integral multiple of the relevant clock period, as determined from the active clock edge. In situations where the apparent Tco is an integral multiple of the period of the relevant clock, a valid output from the device will occur coincident with an active edge of the relevant clock. Since the relevant clock will be a periodic signal, having Tco be an integral multiple of the clock period as determined from the active clock edge is functionally equivalent to having a Tco of zero.
FIG. 2 illustrates a simplified representative version of a conventional approach used to adjust and control Tco. Referring to FIG. 2, portions of a digital device 200 are illustrated. The exemplary simplified device 200 includes an externally accessible input pin 210, a digital clock manager (“DCM”) circuit 220, and a clock distribution buffer 230. The conventional approach involves the use of an input pin 210 to receive an externally-supplied clock signal, a dual data rate (“DDR”) flip-flop 240, and an externally accessible output pin 250. Pin 250 may be a bi-directional input/output pin and may be associated with appropriate buffer and driver circuitry. In operation, an externally-supplied periodic clock signal (not illustrated) is provided to the input pin 210. While not necessarily reflecting any specific structure, boxes 260 and 270 are provided to reflect sources of signal propagation delay encountered in transmitting the various signals described herein.
In operation, as mentioned above, an externally supplied periodic clock signal is provided at the input pin 210 of the clocked digital device 200. The received clock signal is then connected from the input pin 210 to the input (IN) of DCM circuit 220. Because the clock signal will be subject to various internal delays, delays that may vary depending on manufacturing or operating conditions, the clock signal received at the input (IN) of DCM circuit 220 will not typically be exactly aligned with the clock signal actually received at the input pin 210. The DCM circuit 220 receives the clock signal at its input (IN) and generates and provides an output clock signal at its output (OUT). The clock output signal from the DCM circuit 220 is provided as an input to a clock distribution buffer 230. The clock distribution buffer 230 distributes the received clock signal internally to portions of the digital device 200 in such a manner that the distributed clock signal is aligned, or substantially aligned, at every destination point within the device (low skew). In the example of FIG. 2, the clock signal from the clock distribution buffer 230 is used to clock one or more output registers of the digital device 200.
In FIG. 2, the output of the clock distribution buffer 230 is provided as the clock input to an output DDR register 240 configured with constant values for its rising-edge and falling-edge data inputs. Because of its configuration, and because it treats both the rising and falling edges of its received clock as active, the output of register 240 alternates between a logic “1” high level and a logic “0” low level to produce a periodic clock signal having a period that is substantially the same as the period of the supplied clock signal received at pin 210.
The clock signal provided by the DDR output register 240 is provided to bidirectional (IO) pin 250 and the clock signal at IO pin 250 is provided to the feedback input (FB) of the DCM circuit 220. The clock signal provided to the feedback input of the DCM circuit 220 will be subject to some delay (represented by block 270) such that the clock received at the feedback input to the DCM circuit 220 will not be exactly aligned with the clock signal provided to pin 250.
In operation, the DCM circuit 220 will adjust its output clock signal (OUT) until its input (IN) and its feedback input (FB) receive frequency-matched clock signals having coincident active edges (time-aligned). If the routing delay 260 to which the supplied clock signal is subjected is equal to the routing delay 270 to which the clock at pin 250 is subjected, then the output signal at pin 250 will be aligned with the input signal at pin 210 and the apparent clock-to-out of the digital device 200 will be zero or nearly zero relative to the input clock signal at pin 210. Since the clock distribution buffer 230 is designed for low-skew signal distribution, any other output signal sourced from an output register using the same clock will also exhibit a Tco of zero or nearly zero relative to the input clock signal at pin 210. The net result of this technique is a Tco for output signals, relative to the supplied clock signal received at pin 210, of zero or nearly zero. And because of the dynamic adjustment implemented by the DCM circuit 220, this value of Tco will exist independent of variations in process, temperature or voltage.
There are several drawbacks to the simplified compensation circuit of FIG. 2. As one example, the ability of the circuit to produce a Tco that is at, or nearly at, zero hinges on the assumption that the routing delay 260 experienced by the supplied clock signal received at pin 210 is identical to the routing delay 270 experienced by the clock signal provided to pin 250. In practice, such routing delays are almost never identical. Moreover, for a given clocked digital device, it can be difficult or impossible to identify an unused output pin that would be subject to routing delays that are the same, or substantially the same, as those for the supplied clock signal. Even if the routing delays are initially the same or similar, they may not be subject to the same variations as a result of manufacturing and/or operating conditions. As such, there will be differences between the routing delays 260 and 270 and the illustrated representative circuit will not be able to compensate for those variations. Further still, this simplified compensation technique does not provide any mechanism to calibrate Tsu and Th characteristics for a given device.
Accordingly, what is needed is a more effective and efficient way to dynamically adjust and control the clock-to-output time, setup time, and hold time for one or more outputs of a clocked digital device.